A parasitic capacitance may be formed between nodes of a memory cell of a NOR flash memory array. As the size of the memory array increases with an increase in a memory capacity, the parasitic capacitance may also increase. This increased parasitic capacitance may affect applying/discharging of an erase voltage in an erase operation.
FIG. 2 is a block diagram illustrating an example structure of a NOR flash memory device. In FIG. 2, a controller 210 may perform programming sequence control, a read operation, and an erase operation based on a command decoded by a command interface 220. A boosted voltage obtained from an internal voltage control circuit 230 by boosting a power supply voltage may be used for programming and erasing data. The internal voltage control circuit 230 may be controlled by the controller 210 according to each operation mode. An output of the internal voltage control circuit 230 may be supplied to a word line or a bit line through a row decoder 243 or a column decoder 246 of a memory cell array 240.
The memory cell array 240 may include memory cells arranged in matrix form, and each memory cells may have a floating gate type field effect transistor (FET) connected to a word line and a bit line. A row decoder circuit may be used to drive a control gate of each memory cell. The floating gate type FET may include a source and a drain formed in a first conductivity type well provided in a second conductivity type well of a semiconductor substrate, a floating gate formed on the semiconductor substrate between the source and the drain with an insulating layer interposed therebetween, and a control gate formed on the floating gate with an insulating layer interposed therebetween. For example, the source and drain may be formed in a P-well provided in an N-well of the semiconductor substrate
In an erase method of a flash memory, for example, in a substrate erase method, the controller 210 may control a negative voltage boosting circuit 233 and a positive voltage boosting circuit 236 of the internal voltage control circuit 230. For example, the controller 210 may set a gate voltage Vg to be a negative voltage (for example, approximately −9V), control opening of the source and the drain, and set a substrate voltage Vb to be a positive voltage (for example, from approximately 5V to approximately 9V) so that electrons accumulated in the floating gate may be discharged to the substrate. After the accumulated electrons are discharged for a given amount time, the controller 210 may control a negative voltage discharge circuit (not shown) so that a word line voltage may be restored to 0V, thereby ending the erase operation.
FIG. 4 is an example circuit diagram of a negative potential discharge circuit. In FIG. 4, first and second PMOS transistors 15 and 16 and first and second NMOS transistors 17 and 18 may be connected in series. A source of the first PMOS transistor 15 may be connected to a power supply terminal and a source of the second NMOS transistor 18 may be connected to a ground terminal. A gate of the first PMOS transistor 15 may be connected to an output terminal of an inverter 14, and a first discharge timing signal T1 may be input to an input terminal of the inverter 14. Gates of the second PMOS transistor 16 and the first NMOS transistor 17 may be connected to the ground terminal. A second discharge timing signal T2 may be input to a gate of the second NMOS transistor 18. A drain of the second NMOS transistor 18 may be connected to an output terminal 19.
In the example negative potential discharge circuit of FIG. 4, the output terminal 19 may be connected to a load charged to a negative potential, and the negative potential may be discharged to approximately 0V. For example, when the first discharge timing signal T1 is input to the input terminal of the inverter 14, the first PMOS transistor 15 may be turned on. Simultaneously, the second PMOS transistor 16 and the first NMOS transistor 17, which may be used to protect against a withstand voltage, may be turned on. Therefore, the negative potential of the load may be discharged to the power supply voltage Vcc. The discharge may stop at a level which may be lowered by a threshold voltage Vth of the first NMOS transistor 17. For example, the discharge may stop at −Vth. When the second discharge timing signal T2 is input to the gate of the second NMOS transistor 18, the potential of the load may be discharged to ground, and this discharge may stop at approximately 0V.
A discharge rate of the load may be determined based on sizes of the first PMOS transistor 15 and the first and second NMOS transistors 17 and 18. However, when the power supply voltage Vcc supplied externally changes, this may affect the discharge rate. For example, when a word line of a NOR flash memory is discharged, N-well/bulk potential coupling may make it difficult to discharge at a constant rate and prevent overshoot.